Data switches constitute the core of common Ethernet switches, IP routers, multiservice platforms, various transmission network elements and legacy communication equipment. Buffering within the switches normally serves to resolve problems like congestion and contention among switch ports. Various buffering schemes have been developed for this purpose. For example, U.S. Patent Application Publication 2006/0155938, whose disclosure is incorporated herein by reference, describes a shared-memory switch fabric architecture. A shared memory has a plurality of receive ports and a plurality of transmit ports. A memory includes a plurality of memory banks organized in rows and columns. Non-blocking receive crossbar circuitry is operable to connect any of the receive ports with any of the memory banks. Non-blocking transmit crossbar circuitry is operable to connect any of the memory banks with any of the transmit ports. Buffering is operable to decouple operation of the receive and transmit ports from operation of the memory array. Scheduling circuitry is operable to control interaction of the ports, crossbar circuitry, and memory array to effect storage and retrieval of the data segments in the shared memory.